1. Field of the Invention
The present invention relates to a microcomputer that is effective for debugging in a real working environment, and more particularly, it relates to a microcomputer that collects trace information at a plurality of times in a debugging operation while decimating it at a predetermined time period as well as a debugging system for controlling the debugging by the microcomputer and a method for collecting such trace information.
2. Description of Related Art
Upon development of a microcomputer system, verification of its operation and debugging of its software may be commonly performed by a so-called debugger, which is a development support device using any debugging tool such as an ICE (In-Circuit Emulator). The ICE comprises features for substituting for a CPU or a program memory to be developed and for debugging programs and hardware efficiently. For example, such features may include a real-time trace feature that verifies executing conditions in real time, a break feature that stops running at a given address, a single-step feature, a feature for setting data in a register, and the like.
Further, the ICE has a memory mapping feature that stores a program under development on its own memory instead of memory on the microcomputer system to verify the operation of the program. It allows debugging of the program and hardware while executing the developed program both on the ICE main unit and on the system to be evaluated, enabling efficient debugging work.
However, there have been appeared various problems with using the debugger comprising the above ICE, as a result of the fact that working frequencies of microcomputers have increased and that, at present, a CPU, a memory element and peripheral feature blocks may be often contained in one chip with advancement of LSI higher integration technology.
More specifically, for example, increase of a working frequency of a microcomputer may cause delay in signal transmission between the ICE main unit and the microcomputer to be evaluated, which may interfere with real-time trace. In particular, signal delay in a path between the ICE main unit and the microcomputer to be evaluated or in a buffer that stores trace information read out from the microcomputer by the ICE may significantly affect the real-time trace. Consequently, it becomes more difficult to perform the real-time trace that monitors access by the CPU to an external bus at the clock frequency at which the actual microcomputer runs.
In addition, miniaturization and diversification of microcomputers with advancement of LSI higher integration technology affect prices of probes that connects the ICE main unit to a printed circuit board on which the microcomputer to be evaluated is installed. For example, even a microcomputer having same architecture may have different number of pins and different circuit arrangement if its peripheral features are implemented by different circuits, thereby necessitating development of corresponding probes. Further, by miniaturization of microcomputers, it becomes necessary to use expensive adaptors to connect the above probes, which may cause cost-related problems.
As means for solving the above problems, a debugging system has been developed, wherein a debugging feature is incorporated in a microcomputer itself and exchanges debugging information with a debugger via pins dedicated for debugging. An example of such debugger is a microcomputer that is compliant with JTAG (Joint Test Action Group) in which a debugging feature is incorporated.
In the microcomputer compliant with JTAG, shift registers called cells are arranged between an internal logic circuit and each pin, which can monitor signals passing there or inject any data into the signals. Thus, the cells have features equivalent to those of the test probes in conventional testing methods.
FIG. 14 is a diagram schematically showing a configuration of a conventional debugging system as mentioned above, wherein the debugging features are incorporated in the microcomputer compliant with JTAG. In this figure, there is shown a host computer 100 for controlling a debugging tool 101, which can perform various configuration settings for debugging and which sends setting information to the debugging tool 101. The debugging tool 101 exchanges debugging information and trace information with a microcomputer with built-in debugging features 103 via pins that are dedicated for debugging and compliant with JTAG. The pins dedicated for debugging include five JTAG interface pins consisting of a TCK pin (a clock input pin) specified by IEEE 1149.1, a TDI pin (a pin for serially inputting test instruction code or test data), a TDO pin (a pin for serially outputting test instruction code or test data), a TMS pin (a pin for inputting selection of a test mode that controls state transition in a logic circuit to be evaluated in the microcomputer 103), and a TRST pin (a pin for inputting test reset that asynchronously initializes the logic circuit to be evaluated in the microcomputer 103).
Besides, there are pins to output signals from a debugging features block 106 to the debugging tool 101 including a TRCLK pin (a trace clock pin for outputting trace clock signals from the debugging features block 106 to a debugger 102), a TRSYNC pin (a trace synchronization pin for outputting a signal that indicates a leading location of a packet constituting trace information), and a TRDATA pin (a trace outputting pin for outputting the trace information). The debugger 102 equates to a configuration consisting of the host computer 100 and the debugging tool 101. The microcomputer with built-in debugging features 103 comprises the debugging features block 106 that provides the debugging features as well as a CPU 104 and a memory-peripheral features block 105 in one chip. Further, there are shown the CPU 104 for the microcomputer 103, the memory-peripheral features block 105 for the microcomputer 103, and the debugging features block 106 that performs debugging under control of the debugger 102.
FIG. 15 is a block diagram showing a configuration of the microcomputer with built-in debugging features 103 in FIG. 14. In this figure, a jump requesting signal 104a is output from the CPU 104 to a trace controlling section 109 to specify a branch-target address according to a branch instruction executed by the CPU 104. An executed instruction size signal 104b is output from the CPU 104 to the trace controlling section 109 to specify size of an instruction executed from the previous branch. A JTAG controlling section 107 that controls the debugging features by communicating with the debugging tool 101 via the JTAG interface is comprised of control registers that is related to debugging and accessible via the JTAG interface, a TAP (Test Access Port) controller that controls access via the JTAG interface, and the like. Trace trigger generating unit 108 generate a trace start signal 108a, a trace end signal 108b and data access detection signal 108c for controlling trace operation of the trace controlling section 109. The trace start signal 108a instructs the trace controlling section 109 to start outputting trace information, the trace end signal 108b instructs the trace controlling section 109 to finish outputting the trace information, and the data access detection signal 108c specifies the address that the CPU 104 has accessed and the data read therefrom or written thereto. The trace controlling section 109 generates the trace information that traces an internal state of the microcomputer 103 and outputs it to the debugging tool 101, and an address bus 110a and a data bus 110b transfer address signals and data in the microcomputer 103, respectively. It is to be noted that elements similar to those in FIG. 14 are given like reference numerals and description of these elements is thus omitted.
FIG. 16 is a block diagram showing a configuration of the trace controlling section in FIG. 15. In this drawing, a trace controlling circuit 111 receives trace-related information from outside and controls trace operation. A latch signal 111a is generated by the trace controlling circuit 111 to allow a buffer 113 to latch the address on the address bus 110a and data on the data bus 110b. An output controlling section 112 controls outputs from the trace controlling section 109 and outputs the trace clock signal TRCLK, the trace synchronization signal TRSYNC and the trace output TRDATA to the debugging tool 101. The buffer 113 latches information from the address bus 110a and the data bus 110b to create the trace information. A FIFO buffer 114 constitutes the output controlling section 112 and outputs the trace information in a predetermined bit unit from the buffer 113 to the debugging tool 101. Here, it is also to be noted that elements similar to those in FIG. 14 and FIG. 15 are given like reference numerals and description of these elements is omitted.
Next, the operation of the conventional debugging system will be described.
Here, a case will be described wherein execution of a program by the CPU 104 in the microcomputer with built-in debugging features 103 is traced in real time. First, as shown in FIG. 14, the microcomputer 103 is connected to the debugging tool 101 via the pins dedicated for debugging and compliant with JTAG. Then, the user uses the debugger 102 to download the program to be evaluated, which is stored on the memory-peripheral features block 105 in the microcomputer 103. It allows the user to determine trace conditions for the above program to be evaluated and make settings of the trace-related information according to the above conditions using the host computer 100. For example, when the CPU 104 executes the program to be evaluated, address information, which is stored in the memory space of the microcomputer 103 and acts as a trigger to start or end collection of the trace information and so on, is configured. This information is sent to the debugging tool 101 by the host computer 100.
The debugging tool 101 sets the above information via the pins dedicated for debugging and compliant with JTAG on a trace register (not shown) that is one of cells in the JTAG controlling section 107. The CPU 104 in the microcomputer 103 executes the program to be evaluated in response to an instruction from the debugger 102. At this time, the CPU 104 outputs the above information set in the trace register to the trace trigger generating unit 108 via the buses 110a, 110b. Using this information, the trace trigger generating unit 108 generates the trace start signal 108a, the trace end signal 108b and the data access detection signal 108c and outputs them to the trace controlling section 109.
In the trace controlling section 109, the trace controlling circuit 111 therein asserts the above trace start signal 108a to start outputting the trace information. More specifically, for example, when the CPU 104 executes a branch instruction in the above program to be evaluated, it generates the jump requesting signal 104a that specifies the branch-target address and the executed instruction size signal 104b that specifies the size of the instruction executed from the previous branch and outputs them to the trace controlling circuit 111. The trace controlling circuit 111 asserts the jump requesting signal 104a to output the latch signal 111a to the buffer 113. It allows the branch-target address to be taken in the buffer 113 via the address bus 110a. At this time, the trace controlling circuit 111 outputs the executed instruction size signal 104b to the buffer 113.
From the executed instruction size signal 104b, the trace controlling circuit 111 acquires the size of the instruction executed from the previous branch and sets it in the buffer 113. It allows the branch-target address to be taken in the buffer 113 from the address bus 110a sequentially, and therefore the branch trace information that traces each branch-target address and the size of the instruction executed from the previous branch in execution process of the program to be evaluated in the CPU 104 is generated. By outputting the branch-target address and the size of the instruction executed from the previous branch, the branch-source address and the branch-target address of the program can be notified. The branch trace information is output from the buffer 113 to the FIFO buffer 114. Then, the output controlling section 112 outputs the branch trace information in the FIFO buffer 114 by 8 bits at a time to the debugging tool 101 via the TRDATA pin. The output controlling section 112 also outputs the trace clock signal (TRCLK) as well as the trace synchronization signal (TRSYNC) that indicates a leading location of a packet constituting the branch trace information to the debugging tool 101 via respective pins.
On the other hand, when the trace controlling circuit 111 asserts the above data access detection signal 108c, it outputs the latch signal 111a to the buffer 113. At this time, via the address bus 110a and the data bus 110b, the address accessed by the CPU 104 as well as the data read therefrom and written thereto is acquired by the buffer 113 and then the data trace information comprised of the accessed address and the corresponding data is created. The data trace information is output from the buffer 113 to the FIFO buffer 114.
After that, the output controlling section 112 outputs the data trace information in the FIFO buffer 114 by 8 bits at a time to the debugging tool 101 via the TRDATA pin. The output controlling section 112 also outputs the trace clock signal (TRCLK) as well as the trace synchronization signal (TRSYNC) that indicates a leading location of a packet constituting the branch trace information to the debugging tool 101 via respective pins.
Finally, when the trace controlling circuit 111 asserts the above trace end signal 108b, it stops outputting the latch signal 111a to the buffer 113 to stop outputting the trace information.
As described above, the debugger 102 can acquire execution sequence and data access sequence of the evaluated program by the CPU 104 in the microcomputer 103 in real time from the branch trace information and the data trace information. By utilizing such information, the debugger 102 can debug the microcomputer in real time.
The conventional microcomputer of the above-described construction has such a problem that the trace information may not be output fully in case of successive branches and the like, in other words, a so-called overflow of the trace information may occur, thereby adversely affecting the real-time trace of the program.
The above problem will be described more specifically. For example, assuming that one unit of the trace information is comprised of 72 bits and the debugging features block 106 outputs the above trace information by 8 bits at a time from the TRDATA pin, it takes 9 clocks to output the one unit of the trace information. Here, if new branch occurs within 9 clocks after the immediately proceeding branch, the branch-target address of the newly created branch trace information is output from the buffer 113 to the FIFO buffer 114 while the previous branch trace information including the immediately proceeding branch-target address is still output from the FIFO buffer. Consequently, the immediately proceeding branch-target address is overwritten by the new branch-target address of the next created branch, and as a result, both of the address information can not be output in a complete form.
In this regard, it may be contemplated to solve this problem by increasing the outputting speed of the trace information by the debugging features block 106. However, it is difficult to increase the trace clock (TRCLK) frequency in comparison with acceleration of access of the CPU 104 to the memory-peripheral features block 105, because the trace information is output via the external pin (TRDATA pin).
Further, it may be also contemplated to output the trace information in parallel by using multiple external pins (TRDATA pins), but it is not appropriate because it may increase a cost of the microcomputer 103 and moreover restrict miniaturization of its size.